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All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter.
Mitsutoshi Yahara
Kuniaki Fujimoto
Hirofumi Sasaki
Takashi Shibuya
Yoshinori Higashi
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2006)
Keyphrases
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end to end delay
high speed
power consumption
high levels
phase locked loop
image processing
digital libraries
digital technologies