High Speed Reconfigurable FPGA Based Digital Filter.

Navaid Z. Rizvi Raaziyah Shamim Rajesh Mishra Sandeep Sharma

Published in: QSHINE (2013)

Keyphrases

high speed
hardware implementation
field programmable gate array
low power
neural network
low cost
smart camera
efficient implementation
hardware architecture
frame rate
preprocessing step
high speed networks
filtering method
median filter
noise reduction
general purpose
multiscale