EJ-FAT Joint ESnet JLab FPGA Accelerated Transport Load Balancer.

Stacey Sheldon Yatish Kumar Michael Goodrich Graham Heyes

Published in: INDIS@SC (2022)

Keyphrases

power reduction
load balancing
hardware implementation
field programmable gate array
joint estimation
real time
high speed
fpga implementation
low cost
signal processing
genetic algorithm
hardware design
single chip
hardware architecture
real time image processing
parallel hardware