Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks.

Shreesha Srinath Katherine Compton

Published in: FPGA (2010)

Keyphrases

hardware implementation
field programmable gate array
automatically generate
hardware software
scientific computing
floating point
block size
type ii
smart camera
high reliability
fractal image coding
hardware design
dct coefficients
high efficiency
generation method
multiresolution
case study
small sized
data sets