A 5.16Gbps decoder ASIC for Polar Code in 16nm FinFET.
Xiaocheng LiuQifan ZhangPengcheng QiuJiajie TongHuazi ZhangChangyong ZhaoJun WangPublished in: ISWCS (2018)
Keyphrases
- reed solomon
- error control
- integrated circuit
- low complexity
- source code
- error correction
- ldpc codes
- application specific
- fourier transform
- hardware architecture
- low density parity check
- xilinx virtex
- decoding process
- turbo codes
- distributed video coding
- video codec
- error concealment
- hardware implementation
- circuit design
- rotation invariant
- video coding
- motion estimation