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A Low Power All-Digital PLL With -40dBc In-Band Fractional Spur Suppression for NB-IoT Applications.
Na Yan
Lei Ma
Yongxin Xu
Sizheng Chen
Xusong Liu
Junhui Xiang
Hao Min
Published in:
IEEE Access (2019)
Keyphrases
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low power
mixed signal
high speed
low cost
power consumption
vlsi circuits
high power
single chip
wireless transmission
logic circuits
multi channel
vlsi architecture
digital signal processing
low power consumption
image sensor
cmos technology
power dissipation
naive bayes
gate array
general purpose
data management