Design of Charge Pump for Low Power, Wide Range PLL in 65nm CMOS Technology.
Edwin C. CuizonMarven A. YusonAileen B. CaberosNieva M. MapulaHarreez M. VillaruzPublished in: ISCIT (2023)
Keyphrases
- cmos technology
- low power
- power consumption
- high speed
- low cost
- power dissipation
- low voltage
- single chip
- mixed signal
- low power consumption
- parallel processing
- vlsi architecture
- logic circuits
- gate array
- digital signal processing
- nm technology
- image sensor
- power reduction
- motion estimation
- video data
- silicon on insulator