C
search
search
reviewers
reviewers
feeds
feeds
assignments
assignments
settings
logout
High-Speed LFSR Decoder Architectures for BCH and GII Codes.
Yingquan Wu
Published in:
IEEE J. Sel. Areas Inf. Theory (2023)
Keyphrases
</>
reed solomon
high speed
shift register
error correction
error control
low power
distributed video coding
real time
low complexity
turbo codes
frame rate
unequal error protection
high speed networks
ldpc codes
low density parity check
decoding algorithm
power consumption