Hybrid Multi-tile Vector Systolic Architecture for Accelerating Convolution on FPGAs.
Jay ShahNanditha RaoPublished in: ISCAS (2024)
Keyphrases
- hardware software
- management system
- real time
- image processing
- hardware design
- feature vectors
- fpga implementation
- software architecture
- hybrid learning
- field programmable gate array
- hardware implementation
- systolic array
- convolution kernel
- hardware architecture
- design methodology
- vector space
- feature extraction
- web services
- genetic algorithm