Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller.
Subhomoy ChattopadhyayRakesh PatelPublished in: VLSI Design (2007)
Keyphrases
- low power
- design processes
- cmos technology
- design process
- single chip
- low power consumption
- power consumption
- high speed
- nm technology
- low cost
- engineering design
- vlsi architecture
- design decisions
- logic circuits
- case study
- digital signal processing
- gate array
- power reduction
- power dissipation
- database
- mixed signal
- ultra low power
- design methodology
- formal specification
- software development
- artificial intelligence