Login / Signup

A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range.

Sandipan SinhaManish TrivediJaswinder SinghSriharsha EnjapuriDeepesh GujjarRamesh HalliGirishankar Gurumurthy
Published in: VLSID (2024)
Keyphrases
  • high speed
  • low power
  • power reduction
  • wide range
  • single chip
  • power consumption
  • cmos technology
  • user interface
  • low cost
  • design process
  • memory hierarchy