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Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI.

J. Jeba JohannahReeba KorahG. Maria Kalavathy Sivanandham
Published in: Microelectron. J. (2017)
Keyphrases
  • power consumption
  • power dissipation
  • vlsi circuits
  • low power
  • high speed
  • power management
  • deep learning
  • single chip
  • database
  • genetic algorithm
  • objective function
  • parallel processing
  • vlsi design
  • chip design