Formal verification of bond graph modelled analogue circuits.

William Denman Mohamed H. Zaki Sofiène Tahar

Published in: IET Circuits Devices Syst. (2011)

Keyphrases

formal verification
model checking
model checker
bounded model checking
program slicing
automated verification
symbolic model checking
high speed
asynchronous circuits
delay insensitive
circuit design
analog circuits
analog vlsi
logic circuits
quantum computing
logic synthesis
object oriented