A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 µm CMOS.
Mahdi ShabanyDimpesh PatelP. Glenn GulakPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2013)
Keyphrases
- low power
- low latency
- high speed
- single chip
- cmos technology
- power consumption
- low cost
- ultra low power
- circuit design
- vlsi circuits
- real time
- high throughput
- hardware implementation
- image sensor
- highly efficient
- qr decomposition
- cmos image sensor
- mixed signal
- low power consumption
- computer vision
- design methodology
- pattern recognition
- application specific
- efficient implementation
- low complexity
- end to end
- data acquisition
- nm technology