Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus.

Byung-Soo Choi Dong-Ik Lee

Published in: PATMOS (2003)

Keyphrases

low power
high speed
delay insensitive
high power
single chip
wireless transmission
vlsi architecture
digital signal processing
vlsi circuits
image sensor
frequent patterns
logic circuits
main memory
low power consumption
query processing
real time
multithreading
mixed signal
low cost