The Refresh Efficiency on Difference Processor Cache Architecture.
Zheng LiuWeizhen SunPublished in: ISCSCT (1) (2008)
Keyphrases
- memory hierarchy
- multithreading
- memory access
- memory subsystem
- computational complexity
- memory management
- hit rate
- multi processor
- real time
- parallel architecture
- embedded processors
- management system
- shared memory multiprocessors
- data flow
- highly efficient
- cache misses
- single chip
- instruction set
- prefetching
- caching scheme
- computation intensive
- ibm zenterprise
- processor core