Hybrid hierarchical timing closure methodology for a high performance and low power DSP.
Kaijian ShiGraig GodwinPublished in: DAC (2003)
Keyphrases
- low power
- digital signal processing
- low power consumption
- high speed
- power consumption
- signal processor
- low cost
- single chip
- high power
- wireless transmission
- vlsi architecture
- vlsi circuits
- signal processing
- real time
- cmos technology
- gate array
- design methodology
- logic circuits
- power saving
- asynchronous circuits
- power dissipation
- power reduction
- mixed signal
- delay insensitive
- pattern recognition
- video sequences
- image processing