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Scalable Network-on-Chip Architectures for Brain-Machine Interface Applications.
Xian Li
Karthi Duraisamy
Paul Bogdan
Janardhan Rao Doppa
Partha Pratim Pande
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2018)
Keyphrases
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network on chip
multi processor
routing algorithm
interconnection networks
network simulator
shortest path
multi core processors
shared memory
power dissipation
program execution
packet switched