A VLSI-Based Parallel Architecture for Block-Matching Motion Estimation in Low Bit-Rate Video Coding.
Donglai XuHadj BatatiaReza SotudehPublished in: PDPTA (1999)
Keyphrases
- low bit rate video coding
- parallel architecture
- block matching motion estimation
- video coding
- rate distortion
- hardware implementation
- hardware architecture
- signal processing
- bit rate
- motion estimation
- motion estimation algorithm
- motion compensation
- motion compensated
- parallel processing
- video compression
- motion vectors
- shared memory
- video quality
- efficient implementation
- macroblock
- low bit rate
- parallel implementation
- video codec
- distributed memory
- video sequences
- neural network
- inter frame
- computational complexity
- video coder
- visual quality