Low power full search block matching motion estimation architecture.

Sai K. Sadhu Mohamed A. Elgamel Magdy A. Bayoumi Samia Mashaly

Published in: DCV (2002)

Keyphrases

low power
vlsi architecture
power consumption
high speed
low cost
cmos technology
block matching motion estimation
single chip
mixed signal
hardware architecture
low power consumption
nm technology
real time
logic circuits
signal processor
gate array
power dissipation
multi channel
coding scheme