An FPGA-Based Hardware Accelerator for 2D Labeling.

Xianfu Xu Wenjun Su Bin Li Yini Wei Deyu Kong Hongjie Zeng Xuejun Zhang

Published in: ICBIP (2021)

Keyphrases

field programmable gate array
hardware implementation
hardware architecture
embedded systems
hardware design
image processing algorithms
parallel computing

software implementation
low cost
image segmentation
computing systems
hardware architectures
hardware software
active learning

hardware and software
massively parallel
parallel architectures
high end
application specific
image processing

parallel implementation
hardware software partitioning
real time
unsupervised learning
computer systems
data sets