A Hardware-Friendly Algorithm for Scalable Training and Deployment of Dimensionality Reduction Models on FPGA.
Mahdi NazemiAmir Erfan EshratifarMassoud PedramPublished in: CoRR (2018)
Keyphrases
- single pass
- detection algorithm
- low cost
- dimensionality reduction
- fpga implementation
- hardware implementation
- real time
- training process
- probabilistic model
- parameter estimation
- computational complexity
- simulated annealing
- training phase
- learning algorithm
- objective function
- feature extraction
- k means
- neural network
- high speed
- optimal solution
- dynamic programming
- np hard
- software implementation
- vlsi implementation
- feature space