Verifying Preferential Equivalence and Subsumption via Model Checking.
Ganesh Ram SanthanamSamik BasuVasant G. HonavarPublished in: ADT (2013)
Keyphrases
- model checking
- temporal logic
- formal specification
- formal verification
- description logics
- temporal properties
- finite state
- model checker
- verification method
- automated verification
- pspace complete
- partial order reduction
- np complete
- finite state machines
- bounded model checking
- formal methods
- symbolic model checking
- concurrent systems
- process algebra
- timed automata
- reachability analysis
- epistemic logic
- transition systems
- computation tree logic
- linear temporal logic
- possibility theory
- modal logic