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A novel, high performance and power efficient implementation of 8×8 multiplier unit using MT-CMOS technique.
N. Rajput
M. Sethi
P. Dobriyal
K. Sharma
G. Sharma
Published in:
IC3 (2013)
Keyphrases
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efficient implementation
power consumption
hardware implementation
highly parallel
power management
machine translation
low power
high speed
low cost
active set
analog vlsi
graphics processing units
floating point
power supply
efficient processing
parallel architectures
power dissipation