Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs.
Maher FakihKim GrüttnerMartin FränzleAchim RettbergPublished in: IESS (2013)
Keyphrases
- model checking
- temporal logic
- formal verification
- formal specification
- model checker
- finite state
- temporal properties
- partial order reduction
- computation tree logic
- automated verification
- symbolic model checking
- bounded model checking
- reachability analysis
- concurrent systems
- finite state machines
- epistemic logic
- verification method
- transition systems
- pspace complete
- asynchronous circuits
- deterministic finite automaton
- process algebra
- linear temporal logic
- np complete
- artificial intelligence