An embedded merging scheme for VLSI implementation of H.264/AVC motion estimation modules.
Chuan-Yu ChoShiang-Yang HuangJeng-Neng HwangJia-Shung WangPublished in: ICIP (3) (2005)
Keyphrases
- vlsi implementation
- motion estimation
- video coding
- vlsi architecture
- low complexity
- inter frame
- video encoder
- rate distortion
- variable block size
- coding efficiency
- search range
- bit rate
- motion vectors
- macroblock
- filter bank
- block matching
- computational complexity
- image sequences
- fir filters
- rate control
- high coding efficiency
- video compression
- motion compensated
- spatial domain
- motion compensation
- subband
- building blocks
- motion estimator
- super resolution
- video sequences
- video codec
- video coding standard
- distributed video coding
- coding scheme
- high resolution
- multiscale