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Hardware Architecture of Embedded Inference Accelerator and Analysis of Algorithms for Depthwise and Large-Kernel Convolutions.

Tse-Wei ChenWei TaoDeyu WangDongchao WenKinya OsaMasami Kato
Published in: ECCV Workshops (5) (2020)
Keyphrases
  • hardware architecture
  • data analysis
  • learning algorithm
  • bayesian networks
  • support vector
  • low cost
  • kernel function
  • fourier transform
  • image processing algorithms
  • hardware architectures