A low-power fractional decimator architecture for an IF-sampling dual-mode receiver.
Riku UusikartanoJarmo TakalaPublished in: ISCAS (3) (2004)
Keyphrases
- low power
- vlsi architecture
- power consumption
- low cost
- high speed
- cmos technology
- mixed signal
- nm technology
- digital signal processing
- wireless transmission
- real time
- single chip
- low power consumption
- high power
- logic circuits
- signal processor
- vlsi circuits
- image sensor
- delay insensitive
- digital camera
- vlsi implementation
- power dissipation
- data flow