Power Reduction for FPGA Implementations : Design Optimisation and High Level Modelling.

Shrutisagar Chandrasekaran Abbes Amira

Published in: FPL (2006)

Keyphrases

power reduction
high level
power consumption
low power
design process
single chip
power saving
high speed
graphical models
query processing
embedded systems
case study
hardware implementation
energy efficient
design methodology
power dissipation
data streams
hardware architectures