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Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for Cryptographic accelerators.

Tom EnglishEmanuel M. Popovici
Published in: NOCS (2011)
Keyphrases
  • power dissipation
  • network on chip
  • high speed
  • power consumption
  • design process
  • low power
  • single chip