Extracting low-precision floating-point adders from embedded hard FP DSP Blocks on FPGAs.
Bogdan PascaMartin LanghammerPublished in: ARITH (2023)
Keyphrases
- floating point
- embedded systems
- digital signal processing
- field programmable gate array
- programmable logic
- smart camera
- fixed point
- square root
- signal processing
- instruction set
- sparse matrices
- floating point arithmetic
- watermarking algorithm
- scheduling problem
- hardware implementation
- fast fourier transform
- post processing
- low cost
- data structure
- digital signal processor
- image processing
- computer vision