A Column-Parallel Time-Interleaved SAR/SS ADC for Computing in Memory with 2-8bit Reconfigurable Resolution.
Yuandong LiLi DuYuan DuPublished in: AICAS (2023)
Keyphrases
- analog to digital converter
- parallel hardware
- compute intensive
- random access memory
- parallel processing
- coarse grain
- systolic array
- synthetic aperture radar
- high resolution
- distributed shared memory
- fine grain
- general purpose
- low cost
- reconfigurable architecture
- multicore processors
- hash table
- multi threaded
- memory requirements
- main memory
- multiresolution
- memory usage
- low resolution
- image reconstruction
- shared memory
- parallel execution
- parallel programming
- distributed memory
- parallel computation
- computing power