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Efficient implementation of one and two dimensional digital signal processing algorithms on a multi-processor architecture.
Thomas P. Barnwell III
S. Gaglio
C. J. M. Hodges
Published in:
ICASSP (1979)
Keyphrases
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efficient implementation
multi processor
single processor
program execution
parallel architectures
shared memory
multi core processors
hardware implementation
three dimensional
active set
efficient processing
network on chip
pairwise
signal processing
distributed memory