Optimized Hardware Implementation of Vedic Binary Multiplier using Nikhilam Sutra on FPGA.
Palak YashMansi ThakareBabita JajodiaPublished in: LASCAS (2022)
Keyphrases
- hardware implementation
- field programmable gate array
- digital signal processing
- fpga implementation
- signal processing
- hardware design
- software implementation
- efficient implementation
- low power
- hardware architecture
- dedicated hardware
- image processing algorithms
- image binarization
- fpga device
- pipeline architecture
- hardware software
- pipelined architecture
- memory management
- parallel architecture
- single chip
- low cost
- fpga technology
- software engineering
- general purpose processors
- real time