Low power parallel multiplier with column bypassing.
Mingchen WenSying-Jyan WangYen-Nan LinPublished in: ISCAS (2) (2005)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- single chip
- high power
- vlsi circuits
- wireless transmission
- low power consumption
- parallel processing
- digital signal processing
- vlsi architecture
- cmos technology
- parallel implementation
- logic circuits
- real time
- mixed signal
- delay insensitive
- hardware implementation
- shared memory
- hardware and software
- gate array
- ultra low power