Low-Power and High-Speed Pipelined ADC Using Time-Aligned CDS Technique.
Youn-Jae KookJipeng LiBumha LeeUn-Ku MoonPublished in: CICC (2007)
Keyphrases
- low power
- high speed
- single chip
- low cost
- high power
- power consumption
- wide dynamic range
- real time
- vlsi architecture
- analog to digital converter
- data flow
- low power consumption
- wireless transmission
- delay insensitive
- digital signal processing
- image sensor
- ultra low power
- logic circuits
- vlsi circuits
- mixed signal
- frame rate
- gate array
- general purpose