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A Low-Power Implementation of Asynchronous 8051 Employing Adaptive Pipeline Structure.
Je-Hoon Lee
Young Hwan Kim
Kyoung-Rok Cho
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2008)
Keyphrases
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low power
low cost
power consumption
high speed
vlsi architecture
cmos technology
low power consumption
delay insensitive
high power
vlsi circuits
logic circuits
signal processor
single chip
hardware and software
gate array
ultra low power
message passing
scalable video
real time
parallel processing