Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme.
Yuan RenMichael GansenTobias G. NollPublished in: SoCC (2012)
Keyphrases
- low power
- power consumption
- high speed
- low cost
- successive approximation
- single chip
- low power consumption
- computer simulation
- low complexity
- logic circuits
- vlsi architecture
- vlsi circuits
- digital signal processing
- decision feedback
- cmos technology
- low density parity check
- power reduction
- decoding algorithm
- image sensor
- error concealment