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Settling time of mesochronous clock re-timing circuits in the presence of timing jitter.

Naveen KadayintiAmitalok J. BudkuleyDinesh Kumar Sharma
Published in: ISCAS (2017)
Keyphrases
  • high speed
  • asynchronous circuits
  • image processing
  • genetic algorithm
  • multi agent
  • evolutionary algorithm
  • logic circuits