A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture.
Claudio MucciFabio CampiAntonio DeleddaAlberto FazziMirco FerriMassimo BocchiPublished in: IPDPS (2005)
Keyphrases
- instruction set
- high accuracy
- computationally efficient
- multi processor
- high quality
- real time
- parallel architecture
- high speed
- layered architecture
- systolic array
- memory management
- processing elements
- parallel processing
- management system
- multithreading
- multi core processors
- application specific
- computation intensive