Static low power verification at transistor level for SoC design.
Jérôme LescotVincent BlignyDina MedhatDidier Chollat-NamyZiyang LuSophie BillyMark HofmannPublished in: ISLPED (2012)
Keyphrases
- low power
- single chip
- high speed
- power consumption
- low cost
- low power consumption
- vlsi architecture
- power dissipation
- logic circuits
- digital signal processing
- mixed signal
- gate array
- cmos technology
- ultra low power
- high power
- power reduction
- vlsi circuits
- nm technology
- wireless transmission
- embedded systems
- real time
- design process
- efficient implementation