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Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits.

Weidong KuangPeiyi ZhaoJiann-Shiun YuanRonald F. DeMara
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2010)
Keyphrases
  • asynchronous circuits
  • delay insensitive
  • circuit design
  • error tolerance
  • model checking
  • process algebra
  • low cost
  • high speed
  • cmos technology
  • feature selection