A pipelined systolic architecture for the hardware oriented region based motion estimation algorithm.
Andrea FermoGiovanni L. SicuranzaVojko PahorPublished in: EUSIPCO (2002)
Keyphrases
- motion estimation algorithm
- low bit rate video coding
- parallel architecture
- hardware architecture
- motion compensation
- real time
- hardware implementation
- motion vectors
- motion estimation
- data flow
- motion field
- image segmentation
- video coding
- processing elements
- neural network
- signal processing
- bit rate
- multi layer
- video sequences
- three dimensional