Substream-Centric Maximum Matchings on FPGA.

Maciej Besta Marc Fischer Tal Ben-Nun Dimitri Stanojevic Johannes de Fine Licht Torsten Hoefler

Published in: CoRR (2020)

Keyphrases

high speed
low cost
hardware implementation
error concealment
field programmable gate array
real time image processing
systolic array
social networks
image processing
case study
efficient implementation
single chip
network conditions