Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes.
Jing ZengYangcan ZhouJun LinZhongfeng WangPublished in: ISVLSI (2019)
Keyphrases
- hardware implementation
- fpga implementation
- signal processing
- efficient implementation
- software implementation
- hardware design
- field programmable gate array
- error control
- pipeline architecture
- reed solomon
- hardware architecture
- decoding algorithm
- error correction
- parallel architecture
- ldpc codes
- rotation invariant
- image binarization
- memory management
- general purpose
- frequency domain
- dedicated hardware
- fpga device
- multipath
- pipelined architecture