Bounds on the VLSI layout complexity of homogeneous product networks.
Antonio FernándezKemal EfePublished in: ISPAN (1994)
Keyphrases
- worst case
- upper bound
- network size
- lower bound
- vapnik chervonenkis dimension
- network analysis
- complex networks
- vc dimension
- network structure
- signal processing
- high speed
- low cost
- viral marketing
- network design
- vlsi circuits
- lower and upper bounds
- life cycle
- community detection
- error bounds
- real time
- decision problems
- complex systems
- social networks