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Reduced Latency IEEE Floating-Point Standard Adder Architectures.

Andrew Beaumont-SmithNeil BurgessS. LefrereCheng-Chew Lim
Published in: IEEE Symposium on Computer Arithmetic (1999)
Keyphrases
  • floating point
  • floating point arithmetic
  • square root
  • fixed point
  • sparse matrices
  • instruction set
  • data structure
  • floating point unit
  • probabilistic model
  • memory bandwidth