FPGA implementation of a reconfigurable SPIHT coprocessor.
Maurizio MartinaAndrea MolinoAndrea TerrenoFabrizio VaccaPublished in: ISSPA (2) (2003)
Keyphrases
- fpga implementation
- hardware implementation
- dedicated hardware
- field programmable gate array
- coding scheme
- massively parallel
- compression algorithm
- efficient implementation
- compression scheme
- coding method
- bit plane
- signal processing
- bitstream
- image processing algorithms
- compression ratio
- parallel computing
- compressed images
- visual quality
- subband
- image coder
- computing systems
- image coding algorithm
- image codec
- embedded systems
- image coding
- distributed computing
- image compression
- low memory
- fine grained
- instruction set
- low cost
- general purpose
- image analysis
- image processing