Low-Power Parallel Video Compression Architecture for a Single-Chip Digital CMOS Camera.
Jeff Y. F. HsiehTeresa H.-Y. MengPublished in: J. VLSI Signal Process. (1999)
Keyphrases
- low power
- single chip
- video compression
- cmos image sensor
- mixed signal
- image sensor
- low cost
- power consumption
- high speed
- motion compensation
- video coding
- motion estimation
- analog to digital converter
- motion compensated
- cmos technology
- video data
- parallel processing
- real time
- compression ratio
- signal processor
- nm technology
- low power consumption
- video camera
- motion vectors
- vision system
- power dissipation
- bit rate
- distributed video coding
- digital images