Dispersed Array LDPC Codes and Decoder Architecture for NAND Flash Memory.
Wei ShaoJin ShaChuan ZhangPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2018)
Keyphrases
- flash memory
- ldpc codes
- decoding algorithm
- error correction
- storage devices
- message passing
- low density parity check
- file system
- main memory
- solid state
- random access
- data storage
- embedded systems
- b tree
- small size
- rate allocation
- channel coding
- image transmission
- database systems
- management system
- real time
- data management
- multi dimensional
- motion estimation
- source coding
- low complexity
- low cost
- data structure